An integrated circuit may contain a static random access memory (SRAM) which has a small aspect ration (SAR) cell layout using two stretch contacts in each cell to connect the data node in each inverter to the gate extension of the opposite inverter. Each stretch contact overlaps the gate extension at a location over field oxide. The integrated circuit may also contain n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors which are part of complementary metal oxide semiconductor (CMOS) circuits separate from the SRAM. NMOS transistor in the SRAM and NMOS transistors in the CMOS circuits are formed concurrently, and similarly for PMOS transistor in the SRAM and PMOS transistors in the CMOS circuits. The NMOS and PMOS transistors have sidewall spacers adjacent to the gates which provide a desired separation between source/drain regions and channels of the transistors.